| Data Rate | 400, 533, 667,800 Mbps | 800, 1066, 1333, 1600 Mbps |
| VDD / VDDQ | 1.8V ± 0.1V | 1.5V ± .0.075V(DDR3) |
| Support Density | 256Mb ~ 4Gb | 512Mb ~ 4Gb |
| Bank | 512Mb : 4 Bank / 1Gb : 8 Bank | 8 Bank |
| Data Pre-fetch | 4 bit | 8 bit |
| Package Type | 60FBGA for x4 / x8, 84FBGA for x16 | 78FBGA for x4 / x8, 96FBGA for x16 |
| Interface | SSTL-18 | SSTL-15 |
| DQS Signaling | Single / Differential | Differential Only |
| Driver Calibration | Off-Chip Driver Calibration | Self calibration with ZQ pin |
| DQS-CLK De-skewing | No | Yes(write Leveling) |
| On Die Termination | Yes | Yes / Dynamic ODT |
| Reset Pin | No | Yes(Soft power-up) |
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